ZigZag

Description:

ZigZag is a hardware architecture (HW)-mapping design space exploration (DSE) framework for deep learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their HW acceleration cost on specialized accelerators through a fast and accurate analytical HW cost estimation model.

A crucial part in this is the mapping of the algorithmic computations onto the computational HW resources and memories. In the framework, multiple engines are provided that can automatically find optimal mapping points in this search space.

More Information:

• Originates from the Edge AI research challenge (FAIR 2019–2023).

• Responsible Research Lead: Marian Verhelst

• Authors: Arne Symons, Linyan Mei,  Pouya Houshmand 

• Programming Language: Python

• Link to the website

• Link to the repository

• Categories: Embedded systems

Publications:

• Mei Linyan, Houshmand Pouya, Jain Vikram, Giraldo Sebastian, Verhelst Marian, "ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators", in Ieee Transactions On Computers, 2021, Vol. 70, iss. 8, pp. 1160 - 1174

• Mei Linyan, Liu Huichu, Wu Tony, Sumbul H Ekin, Verhelst Marian, Beigne Edith, "A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows", in Proceedings of the 2022 Design, Automation & Test in Europe (DATE 2022), 2022, pp. 220 - 225

• Jain Vikram, Mei linyan, Verhelst Marian, "Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks", in Proceedings of IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021.

• Symons Arne, Mei Linyan, Verhelst Marian, "LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation", in Proceedings of IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021, pp. 1 - 4

• Colleman Steven, Verelst Thomas, Mei Linyan, Tuytelaars Tinne, Verhelst Marian, "Processor Architecture Optimization for Spatially Dynamic Neural Networks", in Proceedings of IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021.

• Houshmand Pouya, Cosemans Stefan, Mei Linyan, Papistas Ioannis, Bhattacharjee Debjyoti, Debacker Peter, Mallik Arindam, Verkest Diederik, Verhelst Marian, "Assessment and optimization of Analog-in-Memory-Compute architectures for DNN processing", in Proceedings of IEEE International Electron Devices Meeting 2020, 2020.